(1) Field of the Invention
The present invention relates to a logic level converter circuit for converting an ECL (emitter-coupled logic) level signal into a TTL (transistor transistor logic) level signal or a CMOS (complementary MOS transistor) logic level signal and, more particularly, to a logic level converter circuit utilizing Bipolar-CMOS (BiCMOS) techniques.
(2) Description of the Related Art
A typical example of a conventional logic level converter circuit utilizing BiCMOS techniques, to which the present invention relates, in shown in FIG. 1. This circuit comprises a differential comparator 10 including a pair of differential NPN-type bipolar transistors Q1, Q2, and a P-channel MOS transistors (hereinafter referred to as "PMOS transistors") T1, T2 whose gates receive from the differential comparator the signals of an in-phase (truth) and an opposite phase (false) with respect to an input signal, respectively, and a current-mirror circuit including N-channel MOS transistors (hereinafter referred to as "NMOS transistors") T3, T4 connected to the drains of the PMOS transistors T1, T2, respectively.
The above conventional logic level converter circuit operates as follows. When an ECL input signal V.sub.IN applied to the base of the bipolar transistor Q1 becomes a high level with respect to a reference voltage V.sub.REF applied to the base of the bipolar transistor Q2, the transistor Q1 turns on and the transistor Q2 turns off. As a result, a voltage drop is developed across a load resistor R1 so as to drive the gate of the PMOS transistor T1 to a low level voltage, thus turning on the PMOS transistor T1. To the contrary, no voltage drop generates across a load resistor R2 connected to the collector of the transistor Q2. Therefore, the gate of the PMOS transistor T2 is held at the high level voltage of a power source voltage V.sub.CC, so that the PMOS transistor T2 is at an off-state. Through the transistor T1, a high level voltage is applied to the gates of the NMOS transistors T3, T4, and an output V.sub.OUT appearing at an output node T.sub.OUT becomes a GND (ground potential) level because the NMOS transistor T4 is turned on and PMOS transistor T2 is turned off.
On the other hand, when the input signal V.sub.IN becomes a low level voltage which is lower than the V.sub.REF voltage, the PMOS transistor T2 turns on and the PMOS transistor T4 turns off. As a result, the output V.sub.OUT at the output node T.sub.OUT becomes a high level whose voltage is approximate to the power source voltage V.sub.CC.
In this way, the conventional logic level converter circuit shown in FIG. 1 performs a level conversion such that it provides a CMOS level as its output V.sub.OUT depending on whether the ECL level input V.sub.IN is at a high level or a low level. In FIG. 1, the symbol I1 represents a constant-current source connected between the ground and the common emitters of the transistors Q1, Q2, the numeral 20 represents a BiCMOS gate which receives the output V.sub.OUT of the logic level converter circuit, and the symbol V.sub.OT represents an output voltage of the BiCMOS gate 20.
This logic level converter circuit shown in FIG. 1 uses the PMOS transistor T2 and the NMOS transistors T4 as output drivers for the output V.sub.OUT. In the case where the output V.sub.OUT changes its voltage from the low to high level, a fast operation is achieved because the gate of the output PMOS transistors T2 is driven directly by the voltage drop developed across the load resistor R2 in the differential comparator 10. However, in the case where it changes from the high to low level, the voltage drop across the load resistor R1 is once received by the inverter constituted by the PMOS and NMOS transistors T1, T3 before being applied to the gate of the output NMOS transistor T4. In this case, therefore, there inevitably occurs undesirable and long propagation delay time. This is a problem to be solved in the conventional circuit.